The invention relates to methods for the manufacture of coatings having low dielectric constants and to devices for the manufacture thereof.
As the dimensions of integrated circuit (IC) devices scale to smaller feature sizes, the resistance-capacitance (RC) delay of the metal interconnect is limiting the performance of high speed logic chips [1, 2]. Up until a decade ago, the resistance caused by interconnects in microprocessors was less than the switching time of transistors, so interconnect resistance was not a factor in microprocessor design. As scaling went into the submicron range, the small size of the wires became an issue. As wires get thinner, their resistance increases. Chip designers responded by switching from aluminum to copper as a material for the interconnects, copper being a superior conductor of electricity. Believing that the integration of low dielectric materials (k<2.5) may be also able to reduce this problem, chip designers have also looked at improving low-k dielectric materials between the wiring levels. Since reduced feature size coincides with a reduction in the distance between current carrying copper interconnects, the reduction in the spacing between the interconnects will cause an increase in cross talk between adjacent wires. Signal degradation as a result of cross talk can be compensated by reducing the dielectric constant of the material separating the interconnecting wires. But despite the presence of a number of candidate materials with dielectric constants k in the range of 2-3 [3], the interconnect issues are becoming increasingly problematic.
The dielectric constant or relative permittivity of a material is dependant on the material structure, polarization and polarizability [4]. A majority of low-k materials are based on a SiO2 or amorphous hydrocarbon (a-C:H) layer [5-7] or on a hybrid layer that is an intermediate between the two. Carbon is less electronegative than oxygen, and hence the introduction of hydrocarbon moieties into SiO2 reduces the dielectric constant. In a similar way, polar Si—OH groups create a large dipole, and although they indicate porosity due to the interruption of the Si—O—Si network, they increase orientational polarization and hence the dielectric constant increases.
It is known that the introduction of voids into the material may effectively reduce density of the material and has a much stronger effect on the dielectric constant than alteration of the polarizability. Most low-k dielectric candidate materials known today [25] are porous. The dielectric constant of silica (kSiO2) is 4, while the dielectric constant of air (kair) is about 1. Notably, dense (i.e. non-porous) materials for semiconductor applications with a dielectric constant below 2.5 are not known [3]. Porous SiO2 layers synthesized from various polyhedral oligomeric silsesquioxane (POSS) precursors [8-10] and prepared using sol-gel deposition techniques have produced thin films with dielectric constants typically between 2-3.
Sol-gel (wet chemical) processes with siloxane precursors have also been extensively studied [11-14], and reports of dielectric constants as low as 1.7 [15] have been reported using tetraethoxysilane (TEOS or tetra-ethyl-ortho-silicate) as a precursor. The low-k properties of these materials are achieved by a combination of low film density and a lowering of the polarizability by incorporation of CH moieties. Post deposition curing of these films can reduce the dielectric [16] constant by driving polar OH groups out of the material, but may also increase it as film densification reduces porosity.
Sol-gel (wet chemical) processes are a popular choice for fabricating low-k materials because they inherently produce porous materials. Materials with void volume fraction as high as 95% have been reported [14]. But despite the fact that highly porous materials with low dielectric constants have been obtained, their susceptibility and weakness make the low-k materials produced by sol-gel processes presently unsuitable for implementation into semiconductor processing.
Various problems are associated with porous SiO2 layers. The porosity of these materials introduces technical problems when they are implemented into copper based interconnect integrated circuits (ICs). Porous materials are mechanically weak compared to dense materials, and porous materials are susceptible to damage during subsequent processing. In addition, porous materials are sensitive to wet and dry cleaning chemicals and they hold volatile compounds that when liberated contaminate subsequent processing steps [26]. Porous materials are also susceptibility to copper diffusion. For an overview of issues concerning the implementation of these porous materials in semiconductor processes reference is made to references [27-30] cited herein.
Gas phase technologies are an attractive alternative to wet chemical processes as they utilize existing vacuum reactors and toolsets in the semiconductor industries and can therefore be easily implemented into existing semiconductor processes. However, gas phase deposition techniques typically produce dense deposits. Synthesis of porous SiO2 layers from siloxane precursors using expanding thermal plasma sources [17], plasma-enhanced chemical vapor deposition (PECVD) [18, 19] and reactive evaporation of SiO [20] have all been investigated, but only materials with k values of between 2.5-3 could be produced.
More recently Grill et al. [21, 22, 23, 24] attempted to synthesize porous low-k films by incorporating volatile organic hydrocarbon fragments into siloxane layers. By removing the volatile hydrocarbon fragments in a 400 ° C post deposition annealing procedure, Grill et al. were able to produce porous layers exhibiting dielectric constants as low as 2.1. Unfortunately, conventional gas phase technologies offer insufficient control over the deposition chemistry and therefore less control over film structure and consequently polarizability. A drawback of the method of Grill et al. is that a post deposition curing is required, making the process more complex.
It is an object of the present invention is to provide methods for the application of a low-k coating that obviate the problems of the prior art.
It is another object of the present invention to provide a method for the implementation of a low-k coating into copper based interconnect integrated circuits with less technical problems.
It is yet another object of the present invention to provide a low-k coating having improved mechanical strength.
It is yet another object of the present invention to provide a low-k coating that is less susceptible to damage during subsequent processing.